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 Freescale Semiconductor, Inc.
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MC13191/D Rev. 1.0, 05/2004 2.4 GHz, Low Power Transceiver
MC13191
(Scale 1:1)
Package Information Plastic Package Case 1311-03 (QFN-32)
Freescale Semiconductor, Inc...
Ordering Information
Device MC13191 Device Marking 13191 Package QFN-32
Contents
1 2 3 4 5 6 7 8 Features . . . . . . . . . . . . . 2 Block Diagrams . . . . . . . 3 Theory of Operation . . . 4 Electrical Characteristics 5 Functional Description 8 Contact Connections . 11 Applications Information 15 Packaging Information 18
The MC13191 is a short range, low power, 2.4 GHz band transceiver designed for low-cost, simple point-to-point and star network applications. The MC13191 includes a complete packet modem capable of formatting data into packets with 125 byte payload. It has an over the air data rate of 250 kbps using O-QPSK modulation and Direct Sequence Spread Spectrum (DSSS) coding. When combined with an appropriate microcontroller unit (MCU) as a baseband processor, the MC13191 provides a complete and cost effective wireless node for point to point and simple star network applications. Interface with the MCU is accomplished via a four wire serial peripheral interface (SPI) which allows interface to a variety of processors. Applications include: * * * * * Security - wireless security systems Medical/Personal Health Care - patient monitoring PC Peripherals - Human Interface Devices (HID) such as keyboards, mice, joysticks, etc. Toys - wireless and interactive toys Vertical proprietary applications
Motorola reserves the right to change or discontinue this product without notice. (c) Motorola,Inc.,2004.All rights reserved.
Features
Freescale Semiconductor, Inc.
1 Features
* * * * * * * Recommended power supply range: 2.0 to 3.4 V 16 Channels 0 dBm (Typical), up to 3.6 dBm maximum output power Buffered Transmit and Receive Data Packets for Simplified Use with Low Cost Microcontrollers Supports 250 kbps O-QPSK Data in 2.0 MHz Channels and Full Spread-Spectrum Encode Link Quality and Energy Detect functions Three Power Down Modes for Power Conservation: -- < 1 A Off Current -- 3.0 A Typical Hibernate Current -- 40 A Typical Doze Current
Freescale Semiconductor, Inc...
* * * * * *
RX sensitivity of -91 dBm (Typical) at 1.0% Packet Error Rate Two internal timer comparators are available to reduce MCU resource requirements Clock output is available for use by MCU Seven General Purpose Input/Output ports (GPIO) are available Operating Temperature Range: -40C to 85C Small form factor QFN-32 Package: -- Meets Moisture Sensitivity Level (MSL) 3 -- 260C Peak Reflow temperature -- Meets lead free requirements
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Block Diagrams
2 Block Diagrams
Figure 1 shows a simplified block diagram of the MC13191. Figure 2 shows the basic system block diagram for the MC13191 in an application. Interface with the IC is accomplished through a 4-wire Serial Peripheral Interface (SPI). The application software resides on the host processor. The host can be anything from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements.
Symbol Synch & Det
Correlator
LNA RFIN+ RFIN-
1st IF Mixer IF = 65 MHz
2nd IF Mixer IF = 1 MHz PMA
Decimation Filter
Baseband Mixer
Matched Filter Power-Up Control Logic
Analog Regulator Digital Regulator L Digital Regulator H XTAL Regulator Receive Packet RAM Receive RAM Arbiter VCO Regulator
VDDA VBATT VDDINT
CCA
DCD
Packet Processor
VDDD
VDDVCO
Freescale Semiconductor, Inc...
AGC Programmable Prescaler Sequence Manager (Control Logic)
RXTXEN
VDDLO2
256MHz
/4
24 bit Event Timer
2 Programmable Timer Comparators
SERIAL PERIPHERAL INTERFACE (SPI)
CE MOSI MISO SPICLK ATTN RST
XTAL1 XTAL2
XTAL O SC
16MHz
Synthesizer
Transmit Packet RAM VCCLO1 2.45GHz VCO Transmit RAM Arbiter Symbol Generation IRQ Arbiter
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 IRQ
PAO+ PAO-
PA
Phase Shift Modulator
MUX
CLKO
FCS Generation
Header Generation
Figure 1. MC13191 Simplified Block Diagram
MC13191 Analog Receiver Digital Transceiver Control Logic SPI and GPIO
Microcontroller SPI Rom (Flash) Timer RAM RAM Arbiter IRQ Arbiter Timer CPU Application A/D
Frequency Generation
Analog Transmitter
Voltage Regulators
Power Up Management
Buffer RAM
Figure 2. System Level Block Diagram
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Theory of Operation
4 bytes
Freescale Semiconductor, Inc.
1 byte 1 byte 125 bytes Max 2 bytes
Preamble
Start of Frame Delimiter
Frame Length
Payload
FCS
Figure 3. MC13191 Packet Structure
3 Theory of Operation
3.1 Packet Structure
Freescale Semiconductor, Inc...
Figure 3 shows the packet structure of the MC13191. Payloads of up to 125 bytes are supported. The MC13191 adds a four byte preamble, a one byte start of frame delimiter (SFD), and a one byte frame length indicator before the data. A Frame Check Sequence (FCS) is calculated and appended to the end of the data.
3.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down conversion stages. The digital back end "de-spreads" the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data. The preamble, SFD, and frame length are parsed and used. A two-byte FCS is calculated and compared to the FCS value appended to the transmitted data, generating a Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 s period after the packet preamble and stored in ROM. The MC13191 processes incoming data as an entire packet. The MCU is notif1ied that an entire packet has been received via an interrupt.
3.3 Transmit Path Description
The transmit path functionality is the exact reverse of the receive path. The data stored in RAM is retrieved, formed into a packet, spread, and then up converted to the transmit frequency. Data is processed as an entire packet and is loaded into the TX buffer. The channel can be checked with the Energy Detect routine which loads a value into SPI. The MCU then requests that the MC13191 transmit the data. The MCU is notified that the packet has successfully been transmitted via an interrupt.
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Freescale Semiconductor, Inc. Electrical Characteristics
4 Electrical Characteristics
4.1 Maximum Ratings
Table 1. Maximum Ratings
Rating Power Supply Voltage Junction Temperature Storage Temperature Range Note: Symbol VBATT, VDDINT TJ Tstg Value 3.6 125 -55 to 125 Unit Vdc C C
Freescale Semiconductor, Inc...
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables. Meets Human Body Model (HBM) = 2 kV and Machine Model (MM) = 200 V except RFin = 100 V MM, PAout = 50 V MM & 1 kV HBM, and VBATT = 100 V MM. RF pins have no ESD protection including PAO + and PAO -.
Note:
4.2 Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Characteristic Power Supply Voltage Symbol VBATT, VDDINT fin TA Vil Min 2.0 Typ 2.7 Max 3.4 Unit Vdc
Input Frequency Ambient Temperature Range Logic Input Voltage Low
2.405 -40 0
25 -
2.480 85 30% VDDINT VDDINT
GHz C V
Logic Input Voltage High
Vih
70% VDDINT -
-
V
SPI Clock Rate RF Input Power Crystal Reference Oscillator Frequency (40 ppm over temperature range)
fSPI Pmax fref
-20
8.0 0
MHz dBm
16 MHz Only
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5
Electrical Characteristics
Freescale Semiconductor, Inc.
4.3 DC Electrical Characteristics
Table 3. DC Electrical Characteristics
(VCC = 2.7 V, TA = 25C, unless otherwise noted) Characteristic Power Supply Current (VBATT + VDDINT) Off Hibernate Doze (No CLKO) Idle Transmit Mode Receive Mode Input Current Low (Vin = 0V) Symbol Ileakage ICCH ICCD ICCI ICCT ICCR Iil Iih Voh Min Typ Max Unit
80% VDDINT 0
<1.0 3.0 40 500.0 34 37 -1.0 1.0 -
VDDINT
A A A A mA mA A A V
Freescale Semiconductor, Inc...
Input Current High (Vin = VDDINT) Output High Voltage
Output Low Voltage
Vol
-
20% VDDINT
V
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Freescale Semiconductor, Inc. Electrical Characteristics
4.4 AC Electrical Characteristics
Table 4. Receiver AC Electrical Characteristics
Characteristic Sensitivity for 1% Packet Error Rate (PER) Saturation (maximum input level) Adjacent Channel Interference for 1% PER (desired signal -82 dBm) Alternate Channel Interference for 1% PER (desired signal -82 dBm) Frequency Error Tolerance Symbol SENSper SENSmax Min Typ -91 0 23 Max Unit dBm dBm dB
-
35
-
dB
-
28
200 80 -
kHz ppm dB
Freescale Semiconductor, Inc...
Symbol Rate Error Tolerance In-band Spurious Reception
Table 5. Transmitter AC Electrical Characteristics
Characteristic Nominal Output Power Error Vector Magnitude Power Control Range Over the Air Data Rate Tbit Symbol Pout EVM Min Typ 0 27 20 250 Max 45 Unit dBm % dB kbps
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Functional Description
Freescale Semiconductor, Inc.
5 Functional Description
5.1 MC13191 Operational States
The MC13191 has a number of operational states that allow for low-current operation. Entry from the Off to Idle state occurs when RST is de-asserted. Once in Idle, the SPI is active and controls the IC. Transition to Off, Hibernate, and Doze is controlled through the SPI. These states are summarized, along with the transition times, in Table 6. Current drain in the various states is listed in Table 3, DC Electrical Characteristics.
Table 6. MC13191 Mode Definitions and Transition Times
Mode Definition All IC functions including SPI Off, Leakage only. RST asserted. Crystal Reference Oscillator Off, SPI not functional. IC Responds to ATTN. Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = 1 for frequencies of 1 MHz or less, SPI not functional. Responds to ATTN and can be programmed to enter Idle State through an internal timer comparator. Crystal Reference Oscillator On with CLKO output available. SPI active. Crystal Reference Oscillator On. Receiver On. SPI should not be accessed. Crystal Reference Oscillator On. Transmitter On. SPI should not be accessed. 144 s from Idle Transition Time To or From Idle 23.332 ms to Idle 18.332 ms to Idle
Freescale Semiconductor, Inc...
Off Hibernate
Doze
332 s to Idle
Idle Receive
Transmit
144 s from Idle
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Freescale Semiconductor, Inc. Functional Description
5.2 Serial Peripheral Interface (SPI)
Control of the MC13191 and data transfers are accomplished by means of a 4-wire Serial Peripheral Interface (SPI). This section details the operation of the SPI.
5.2.1 General
The MC13191 operates as a slave device only. Data to be written into the IC is presented on the Master Out/Slave In (MOSI) pin of the device, while data read from the device is presented to the master device on the Master In/Slave Out (MISO) pin. Synchronization of the data is accomplished by the return-to-zero Serial Clock (SPICLK) input and is framed by the Chip Enable (CE) pin. Data on MOSI is always clocked into the IC on the leading edge of SPICLK and data is clocked out of the IC at MISO on the falling edge of SPICLK. The master device should transfer MISO data to its internal registers on the trailing edge of SPICLK. A typical interconnection to a microprocessor is illustrated in Figure 4.
Freescale Semiconductor, Inc...
MCU
MC13191
Shift Register
RxD TxD Sclk
MISO MOSI SPICLK Shift Register
Baud Rate Generator
Chip Enable (CE)
CE
Figure 4. SPI Interface
MISO is programmable through SPI to be either high impedance (default) or low impedance when CE is negated. Although the SPI is fully static, internal memory, timer and interrupt arbiters require an internal clock, CLKcore, derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory. Figure 5 and Table 7 show the SPI timing diagram and timing specifications.
tCE_SU tCLKH tCLKL tPER tCE_H
CE
SPICLK
MOSI
R/W
Addr 1
Write 0
tSU MISO
tH
tSU
tH Read 1
tSU
tH Read 0
tP1
tP1
Figure 5. SPI Parametric Timing Diagram.
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Functional Description
Freescale Semiconductor, Inc.
Table 7. SPI Parametric Timing Specifications
Symbol 1/tPER tCLKH tCLKL tCE_SU tCE_H tSU
Parameter SPICLK frequency Pulse Width, SPICLK high Pulse Width, SPICLK low Setup Time, CE low to rising SPICLK Hold Time, rising SPICLK to CE high Setup Time, MOSI to rising SPICLK Hold Time, MOSI to rising SPICLK Propagation Delay, MISO to rising SPICLK Propagation Delay, MISO to rising CE
Min
Typ
Max 8.0
Unit MHz ns ns ns ns
0.5 * tPER 0.5 * tPER 0.5 * tPER 1.0 * tPER 0.5 * tPER 0.5 * tPER 0 0
ns ns ns ns
Freescale Semiconductor, Inc...
tH tP1 tP2
NOTE:
The minimum duration of a singular SPI access, at the maximum SPICLK rate of 8 MHz is 3.0s.
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Contact Connections
6 Contact Connections
Table 8. Contact Function Description
Contact # 1 2 3 4 5 Contact Name RFINRFIN+ Not Used Not Used PAO+ RF Output /DC Input RF Output/DC Input Type RF Input RF Input Description LNA negative differential input LNA positive differential input Tie to Ground Tie to Ground Power Amplifier Positive Output. Open drain. Connect to VDDA. Power Amplifier Negative Output. Open drain. Connect to VDDA. Tie to Ground Digital Input/ Output General Purpose Input/Output 4. When digital output: Vol= 20%VDDINT Voh=80%VDDINT When digital input: Vil= 30%VDDINT Vih=70%VDDINT 1 mA max source/ sink. When digital output: Vol= 20%VDDINT Voh=80%VDDINT When digital input: Vil= 30%VDDINT Vih=70%VDDINT 1 mA max source/ sink. When digital output: Vol= 20%VDDINT Voh=80%VDDINT When digital input: Vil= 30%VDDINT Vih=70%VDDINT 1 mA max source/ sink. 2.4 to 2.5 GHz Functionality 2.4 to 2.5 GHz 2.4 to 2.5 GHz
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6
PAO-
2.4 to 2.5 GHz
7 8
Not used GPIO4
9
GPIO3
Digital Input/ Output
General Purpose Input/Output 3
10
GPIO2
Digital Input/ Output
General Purpose Input/Output 2.
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Contact Connections
Freescale Semiconductor, Inc.
Table 8. Contact Function Description (Continued)
Contact # 11
Contact Name GPIO1
Type Digital Input/ Output
Description General Purpose Input/Output1.
Functionality When digital output: Vol= 20%VDDINT Voh=80%VDDINT When digital input: Vil= 30%VDDINT Vih=70%VDDINT 1 mA max source/ sink. Vil= 30%VDDINT Vih=70%VDDINT
12
RST
Digital Input
Freescale Semiconductor, Inc...
Active Low Reset Pin. While held low, the IC is "off" and all internal information is lost from RAM and SPI registers. When high, IC goes to IDLE State, with SPI in default state. Active High. Low to high transition initiates RX or TX sequence depending on SPI setting. If held high (e.g., tied to VBATT), SPI setting start RX or TX sequence. Active Low Attention pin. Transitions IC from either Hibernate or Doze states to Idle. Clock output to host CPU. Programmable frequencies of: 16, 8, 4, 2, 1 MHz, and 62.5 kHz, 32.786+ kHz (default), and 16.393+ kHz External clock input for the SPI interface.
13
RXTXEN
Digital Input
Vil= 30%VDDINT Vih=70%VDDINT
14
ATTN
Digital Input
Vil=30%VDDINT Vih=70%VDDINT
15
CLKO
Digital Output
Vol= 20%VDDINT Voh=80%VDDINT freq=16MHz (20/80 DC) 20 pF. All others (50/50 DC) Vil= 30%VDDINT Vih=70%VDDINT freq= 8 MHz (max) Vil= 30%VDDINT Vih=70%VDDINT freq=8 Mbps (max) Vol= 20%VDDINT Voh=80%VDDINT 1 mA max source/ sink. Vil= 30%VDDINT Vih=70%VDDINT Open drain device. 40 k internal pullup. Interrupt can be serviced every 6 s with <20 pF load. External pullup must be >4 k.
16
SPICLK
Digital Clock Input
17
MOSI
Digital Input
Master Out/Slave In. Dedicated SPI data input.
18
MISO
Digital Output
Master In/Slave Out. Dedicated SPI data output.
19
CE
Digital Input
Active Low Chip Enable. Activates SPI. Active Low Interrupt Request
20
IRQ
Digital Output
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Table 8. Contact Function Description (Continued)
Contact # 21 Contact Name VDDD Type Bypass Description Digital supply bypass
Contact Connections
Functionality Decouple 0.1 to 0.47 F to ground. 2.0 to 3.4 V Decouple 0.47 to 1 F to ground. When digital output: Vol= 20%VDDINT Voh=80%VDDINT When digital input: Vil= 30%VDDINT Vih=70%VDDINT 1 mA max source/ sink. When digital output: Vol= 20%VDDINT Voh=80%VDDINT When digital input: Vil= 30%VDDINT Vih=70%VDDINT 1 mA max source/ sink. When digital output: Vol= 20%VDDINT Voh=80%VDDINT When digital input: Vil= 30%VDDINT Vih=70%VDDINT 1 mA max source/ sink. Connect to 16 MHz crystal and load capacitor Connect to 16 MHz crystal and load capacitor Decouple 100 to 1000 pF to ground Decouple 100 to 1000 pF to ground Decouple 100 to 1000 pF to ground
22
VDDINT
Input
Digital interface supply & digital regulator input - Connect to Battery
23
GPIO5
Digital Input/ Output
General Purpose Input/Output 5
Freescale Semiconductor, Inc...
24
GPIO6
Digital Input/ Output
General Purpose Input/Output 6
25
GPIO7
Digital Input/ Output
General Purpose Input/Output 7
26
XTAL1
Input
Crystal Reference oscillator input
27
XTAL2
Output
Crystal Reference oscillator output
28
VDDLO2
Input/Bypass
LO2 VDD supply - Connect to VDDA externally LO1 VDD supply pad - Connect to VDDA externally VCO regulated supply bypass
29
VDDLO1
Input/Bypass
30
VDDVCO
Bypass
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Contact Connections
Freescale Semiconductor, Inc.
Table 8. Contact Function Description (Continued)
Contact # 31
Contact Name VBATT Input
Type
Description Analog voltage regulators Input Connect to Battery Analog regulated supply Output - Connect to VDDLO1 and VDDLO2 externally External paddle / flag ground
Functionality Decouple 1 F and 100 pF ground Decouple 100 to 1000 pF to ground
32
VDDA
Output
EP
Ground
Connect to ground
32 VDDA
31 VBATT
30 VDDVCO
29 VDDLO1
28 VDDLO2
27 XTAL2
26 XTAL1
25 GPIO7
Freescale Semiconductor, Inc...
1 2 3 4 5 6 7 8
RFINRFIN+ Not Used Not Used PAO+ PAONot Used GPIO4 GPIO3 GPIO2 GPIO1 RST GND
GPIO6 GPIO5 VDDINT VDDD IRQ CE
24 23 22 21 20 19 18 17
MC13191
RXTXEN SPICLK 16 CLKO ATTN
MISO MOSI
9
10
11
12
13
14
15
Figure 6. Contact Connections (Top View)
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Freescale Semiconductor, Inc. Applications Information
7 Applications Information
Figure 7 shows a basic application schematic for interfacing the MC13191 with an MCU. Table 9 lists the Bill of Materials. The MC13191 has differential RF inputs and outputs. These are well suited to balanced PCB antenna structures. Alternatively, chip antennas or other single-ended structures can be used with commercially available chip baluns or microstrip equivalents. PAO+ and PAO- require connection to VDDA, the analog regulator output. This is best accomplished with microstrip lines which are decoupled to act as harmonic traps. The 16 MHz crystal should be mounted close to the MC13192 because the crystal trim default assumes the listed Toyocom crystal and the 9 pF capacitors shown are used. If a different crystal is used, it should have a load capacitance of 9 pF or less. Bypassing capacitors are critical and should be placed close to the device. Unused GPIOs and contacts should be grounded as shown. The SPI connections to the MCU include IRQ, CE, MOSI, MISO and SPICLK. The SPI can run at any frequency of 8 MHz or less. Optionally, CLKO can provide a clock to the MCU. The CLKO frequency is programmable via the SPI and has a default of 32.786+ kHz. The ATTN line can be driven by a GPIO from the MCU or can be negated by a switch or other hardware. The latter approach allows the MCU to be put in a sleep mode and then awakened by CLKO when the ATTN line wakes up the MC13191. RXTXEN can be used to initiate receive or transmit sequences under MCU control. In this case, RXTXEN must be controlled by an MCU GPIO with the optional connection shown. Otherwise, RXTXEN is held high and receive or transmit sequences are initiated by an SPI command. Device reset (RST) can be controlled through an optional connection to an MCU GPIO or by an external pull-down.
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16
C1 9.0 pF C2 9.0 pF Y1 16.00 MHz BATTERY C10 100 pF C7 100 pF IRQ/INT C11 1.0 F Optional 47 k R3 100 k R2 1 M R4 10 k C3 C5 C6 0.1 F 100 pF 100 pF 32 Rx Antenna VDDA XTAL2 XTAL1 GPIO7 VBATT VDDLO1 VDDLO2 VDDVCO 1 RFINGPIO6 GPIO5 VDDINT VDDD IRQ CE MISO MOSI 17 GPIO RXTXEN GPIO2 GPIO1 18 19 CLK 20 21 C4 0.1 F SPICLK 22 23 MOSI RFIN+ Not Used Not Used PAO+ PAONot Used GPIO4 SPICLK GPIO3 ATTN CLKO RST 2 3 4 5 6 7 Tx Antenna Microstip Harmonic Traps 9 C8 100 pF VDDA GPIO ATTN These three GPIO lines are optional MCU connections. 10 11 12 13 14 15 16 GPIO C9 100 pF 8 24 L1 R1 6.8 nH 200 31 30 29 28 27 26 25 GPIO (CE) MISO
Applications Information
U1 MC13191
MCU
Freescale Semiconductor, Inc.
Figure 7. MC13191 Applied With an MCU
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RESET
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Freescale Semiconductor, Inc. Applications Information
Table 9. MC13191 to MCU Bill of Materials (BOM)
Item Number 1 2 3 4 5 6 7 Label/Value 9 pF 9 pF 0.1 uF 0.1 uF 100 pF 100 pF 100 pF 100 pF 100 pF 100 pF 1.0 uF 6.8 nH 200 1 M 100 k 10 k MC13191 16.000 MHz Attributes SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 SMD0201 QFN TOYOCOM TSX-10A, 9 pF load Designation C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 L1 R1 R2 R3 R4 U1 Y1
Freescale Semiconductor, Inc...
8 9 10 11 12 13 14 15 16 17 18
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Packaging Information
Freescale Semiconductor, Inc.
8 Packaging Information
PIN 1 INDEX AREA 0.1 A 0.1 2X C 0.1 G 1.0 0.8 5 (0.25) 0.05 0.00 (0.5) C DETAIL G VIEW ROTATED 90 CLOCKWISE M B SEATING PLANE 1.00 0.75 0.05 C 5 C 5 2X M C
Freescale Semiconductor, Inc...
0.1
C 3.25 2.95
A
B DETAIL M PIN 1 INDEX
EXPOSED DIE ATTACH PAD
25
32
24
1 0.25
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. COPLANARITY APPLIES TO LEADS, CORNER LEADS, AND DIE ATTACH PAD. 6. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12.
3.25 2.95 0.1 C A B 0.217 0.137 17 8 N 16 32X 0.5 0.3 9 32X 0.30 0.18 0.1 VIEW M-M 0.05 M M C C DETAIL S PREFERRED BACKSIDE PIN 1 INDEX (45 5 ) DETAIL S A B (0.25) (0.1) 0.5 28X 0.217 0.137
(1.73)
0.60 0.24
32X
0.065 0.015
(0.25) DETAIL N PREFERRED CORNER CONFIGURATION 4
0.60 0.24 DETAIL N CORNER CONFIGURATION OPTION 4 DETAIL M PREFERRED BACKSIDE PIN 1 INDEX
DETAIL T 0.475 0.425
1.6 1.5
5
BACKSIDE PIN 1 INDEX
(90 )
2X
0.39 0.31
R
0.25 0.15 DETAIL M BACKSIDE PIN 1 INDEX OPTION DETAIL T BACKSIDE PIN 1 INDEX OPTION
2X
0.1 0.0
DETAIL M BACKSIDE PIN 1 INDEX OPTION
Figure 8. Outline Dimensions for QFN-32, 5x5 mm (Case 1311-03, Issue E)
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NOTES
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Freescale Semiconductor, Inc...
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